Binary counting



2 Sheets-Sheet 1 Filed Jan. 21, 1958 Feb. 14, 1961 A. w. CARLSON BINARY couNTmG 2 Sheets-Sheet 2 Filed Jan. 21, 1958 United States Patent() BINARY coUNrrNG Arthur William Carlson, Harrison, Maine, assignor to the United States of America as represented by the Seeretary of the Air Force Filed Jan. 21, 1958, Ser. No. 710,378

3 Claims. (Cl. 307-885) (Granted under Title 35, U.S. Code (1952), sec. 266) The invention described herein may be manufactured and used by or for the United States Government for governmental purposes without payment to me of any royalty thereon.

This invention relates to counting operatons, and particularly to methods and means for registering a count by the processing of electrical pulses having a repetition rate extending into the megacycle range.

Heretofore high speed pulse counters, operating on the two-value principles of the binary code, have been prone to the development of erroneous counts, the error tendency being inherent in the mode of operation, particularly that feature of the count shift process which introduces sharp uctuations in electrical load, from one counting step to the next, Whenever the count sequence is such as to sharply increase or decrease the number of counting stages that must undergo position-reversal in order to register the correct digital total. Thus, if the counting chain consists of tive bistable stages, with each stage being embodied in a two-state binary unit (ip op) the stepping of the count from a given binary value to the next may involve a change in state for only one of the five ip-op units; yet on the very next pulsing step it may be necessary for all five units to undergo reversal-for example, from digital values O-l-l-l-l to 1 0-0-0-0. These sharp variations in pulse patterns, when they occur with micro-second frequency, impose electrical loading problems that are diiiicult to manage, especially when the circuitry includes gating devices for the simultaneous switching of all stages requiring switching on any given count.

The present invention provides a method and means for significantly lessening the incidence of switching transients and spurious pulses in a multi-stage digital counting chain, the method being characterized by incorporating into the counting scheme a count-shifting procedure of novel concept, namely, the concept of electrically gating the ow of stage-changing pulses to the successive binary stages in such manner that not more than two stages of the chain are caused to undergo a change in state to 1, or l to 0) for any single count increment.

Another characteristic of the inventon is the provision of a combination of surface-barrier transistors and pulse gating devices inter-related in a novel circuit structure to achieve the indicated results.

These and other objects and characteristics of the invention will be apparent upon examination of the following description of the embodiment of the invention illustrated in the accompanying drawings wherein:

Fig. 1 is a diagram, in block form, of circuitry ernbodying the invention;

Fig. 2 shows details of the circuitry of Fig. l; and

Figs. 3, 4, and 5 are graphs showing wave forms and pulse patterns characteristic of the circuitry of Fig. l, in actual operation.

Referring rst to Fig. 1, bistable units to 14, inclusive, and gates to 27, inclusive, are inter-related to ICC Counter stage Stages Changing State A B C Initial State.

down to count 16, then change to ls at count 17, con- 4 tinue with thirty-two ls and with the balance Os for the remainder of the count. Here the cycle repeats. ln other Words, with the introduction of a sixth stage, the state of the addition changes at a count where, prior to the step, only the tirst stage of the counter changedV state.

In cycling the counter once, there are two counts where" only the rst stage changes. Therefore, in adding another stage, have it change state at one of these counts, Since the capacity of the counter is doubled with this addition. there are in the enlarged counter two counts with only the rst-stage change.

The code described above is not the only one with the property of a maximum of two stages changing state at a given count because, with exception of the first, one has two choices at each counter stage for the count at which that stage changes. There are ZN-l ways of doing this with the various stages showing patterns of zeros and ones (first stage alternate 0s" and 1s, second stage two "0s and two 1s, etc.) where N is the number of stages.

1n Fig. 1 the rectangular blocks represent the binary For example, if it is desired to' elements of the counter (such as Hip-flops). By a pulse application these binary elements have their state changed. For example, if stage A is in the state where lead A is high and lead low, the application of a pulse to stage A causes a change of state to lead A low .and lead high. The circles. r'epresentgates of which ther'eare 2N-3, where N is the number of stages. The gates are Controlled by the binary elements. The letters labeling. the gates indicate .the stage and lead controlling them. Forexample,the gate marked iscontrolled by the lead of stage B. The arrowheads indicate the path taken by the pulse through a gate when it is enabled. In describing the operation of the counter, it will be assumed that a gate is enabled when the lead controlling it is high. A counter stage will be said to be in the state l if the unprimed lead is high, and in the state if the unprimed lead is low (or the primed lead high). Y Y

WithA all stg's in the'cou'nter initially in the zero state, gates and are enabled. When a'puls'e is obtained from the pulse source, it goes directly-to stage A, changing A to th-e state 1. lt also passes through gates, and but no farther (for the tive-stage, counter undeiicon-Y sideration). After the rst pulse, the stage A isY l and the rest O with gates A, and enabled. Y

The second pulse goes directly to stage A (as do all pulses), changing A to 0. It also passes through gate A to stage B, making B, 1. Gates ,'B, andi) are now enabled. Y Y Y The third pulse changes A to "1 andgg'o'e's'thjrough gates and B to stage C, changingv C-'frcm SiDitto-1. Gates A, B, C, and are enabledffY The fourth Ypulse changes A to 0 and lf3A to 0, enabling gates l'3, C, and D. The circuit continues to cou'nt'in this manner as shown in Fig. 1.1

Fig. 2 is a circuit diagram of tive stages of a seven-stage counter Operating with supply voltages ranging from 1.5 to 4.5 volts (which was not exceeded for fear of damaging thetransistors), and capable of counting 0.1 psec., pulses upto a repetition rate of 4 mc./sec. Fig. 3'is a photograph of the collector waveforms of the first tive stages ofthe counter, counting 0.1 fisec. pulses at l mc. p.r.f.

Fig. 4 is a photograph showing the pulses in the counterv ofFig. 3. In the rst rowV are the l-mc. pulses being counted. The remaining waveforms are the pulses going to the second, third, fourth, and fifth stages in that order from the top. Y l

For comparison with Fig. 3, Fig. 5 shows the collector waveforms of a conventional four-stage binary counter constructed with surface-barrier transistors.

Forpthe purpose of summarizing, the advantages of the hereindisclosed counter are:

(1) Fewer transients than in the ordinary binary counter because only two counter stages at most change state at a given count. Y

V(2) Simultaneous pulsing (coincident with count pulse) when two stages are to change state.

' (3) A lighter and more uniform load on the count pulsesource than in the ordinary binary counter.

(4) Simple gating circuitry.

What is claimed is:

1. An impulse responsive circuit comprising a plurality of iiip-ops having two outputs and' a trigger input, a plurality of coincidence means arranged in pairs, with successive pairs connected to and responsive to the respective outputs of the preceding flip-flop unit, and with one of eachpair of said Vmeans being additionally connected to and responsive to the output of one only of the preceding pair of said coincidence means, and each of said flip-flop trigger inputs being connected to and responsive to the other onlyr Yof the preceding pair of said coincidence means, so that not more than two of said flip-flop units can change'state in any one irnpulse-receiving cycle, and means for priming said coincidence means.

2. A digital counting system including, in combination with a plurality oi ilip-tlopV units and a plurality of pulsegating devices connected serially in a single electrical series circuit in which successive pulse-gating devices occupy positions intermediateV successive ip-op-units, asecond set of pulse-gating devicesY connected serially in a second electrical series circuit, and means including individual shunt circuits for electrically. interconnecting successive flip-flop units with successive pulse-gating devices of said second set, to cause. said second set of pulse-gating devices to'limitthe numhervof'flip-op polarity reversals to not more than two reversals in any single digit-counting cycle.

-3. VA digital. counting system including, in combination with a pluralityrof flip-flop units and a plurality of pulsegating devices connected serially in a single electrical series circuit in which successive pulse-gating devices occupy positions intermediate successive` ilip-op units, a second set of pulse-gating devices connected serially in a second electrical series circuit, and means operable upon said second set of pulse-gating devices to limit the number of Hip-nop polarity reversals to not more than two reversals in any single digit-counting cycle.

References Cited in the tile of this Ypatent UNITED'STATES PATENTS 2,644,887 Wolfe uly 7, 1953 2,823,856 Booth et al. ---a Feb. 18, 1958 2,888,556 Richards May 26, 1959 OTHER REFERENCES 

